Amorphous silicon rram with non-linear device and operation

ABSTRACT

A non-volatile memory device includes a resistive switching device having a first electrode, a second electrode, and a resistive switching element, wherein the resistive switching element comprises a silicon material disposed in an overlapping region between the first electrode and the second electrode, wherein the second electrode comprises at least a metal material physically and electrically in contact with the resistive switching material, wherein the resistive switching element is characterized by a resistance depending on an electric field in the resistive switching element, and a non-linear device coupled between the first electrode and the resistive switching element , wherein the non-linear device is configured to conduct electric current when a voltage greater than a first voltage is applied to the second electrode, wherein the resistive switching device is configured to change from a first state to a second state in response to the first voltage.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application claims priority to and is a continuation of U.S.application Ser. No. 13/174,264, filed Jun. 30, 2011, which is hereinincorporated by reference for all purposes.

STATEMENTS RELATED TO GOVERNMENT OR FEDERALLY FUNDED RESEARCH

Not Applicable

BACKGROUND

The present invention is generally related to resistive switchingdevices. More particularly, embodiments according to the presentinvention provide a method and a structure for forming a resistiveswitching device coupled to a non-linear device. The present inventioncan be applied to non-volatile memory devices but it should berecognized that the present invention can have a much broader range ofapplicability.

The inventors of the present invention have recognized the success ofsemiconductor devices has been mainly driven by an intensive transistordown-scaling process. However, as field effect transistors (FETs)approach sizes less than 100 nm, physical problems such as short channeleffect begin to hinder proper device operation. For transistor basedmemories, such as those commonly known as Flash memories, otherperformance degradations or problems may occur as device sizes shrink.With Flash memories, a high voltage is usually required for programmingof such memories, however, as device sizes shrink, the high programmingvoltage can result in dielectric breakdown and other problems. Similarproblems can occur with other types of non-volatile memory devices otherthan Flash memories.

The inventors of the present invention recognize that many other typesof non-volatile random access memory (RAM) devices have been explored asnext generation memory devices, such as: ferroelectric RAM (Fe RAM);magneto-resistive RAM (MRAM); organic RAM (ORAM); phase change RAM(PCRAM); and others.

A common drawback with these memory devices include that they oftenrequire new materials that are incompatible with typical CMOSmanufacturing. As an example of this, Organic RAM or ORAM requiresorganic chemicals that are currently incompatible with large volumesilicon-based fabrication techniques and foundries. As another exampleof this, Fe-RAM and MRAM devices typically require materials using ahigh temperature anneal step, and thus such devices cannot be normallybe incorporated with large volume silicon-based fabrication techniques.

Additional drawbacks with these devices include that such memory cellsoften lack one or more key attributes required of non-volatile memories.As an example of this, Fe-RAM and MRAM devices typically have fastswitching (e.g. “0” to “1”) characteristics and good programmingendurance, however, such memory cells are difficult to scale to smallsizes. In another example of this, for ORAM devices reliability of suchmemories is often poor. As yet another example of this, switching ofPCRAM devices typically includes Joules heating and undesirably requirehigh power consumption.

From the above, a new semiconductor device structure and integration isdesirable.

BRIEF SUMMARY OF THE PRESENT INVENTION

The present invention is generally related to resistive switchingdevices. More particularly, embodiments according to the presentinvention provide a method and a structure for forming a resistiveswitching device coupled to a non-linear device. The present inventioncan be applied to non-volatile memory devices but it should berecognized that the present invention can have a much broader range ofapplicability.

In a specific embodiment, a non-volatile memory device is provided. Thenon-volatile memory device includes a resistive switching device. In aspecific embodiment, the resistive switching device includes a firstelectrode, a second electrode, and a resistive switching elementdisposed in an intersection region between the first electrode and thesecond electrode. The resistive switching element can include a siliconmaterial in a specific embodiment. In a specific embodiment, the secondelectrode includes at least a metal material physically and electricallyin contact with the resistive switching material. In a specificembodiment, the non-volatile memory device includes a non-linear devicedisposed in between the first electrode and the resistive switchingelement and serially connected to the resistive switching element. Thenon-linear device is configured to conduct electric current when avoltage greater than a first voltage is applied to the second electrode.The first voltage causes the resistive switching device to change from afirst state to a second state in a specific embodiment. Depending on theembodiment, the first state can be a high resistance state and thesecond state can be a low resistance state. Alternatively, the firststate can be a low resistance state and the second state can be a highresistance state.

In a specific embodiment, a method of programming a memory cell in anarray of non-volatile memory devices is provided. The method includesproviding a plurality of memory cells arranged in an array. Each of theplurality of memory cells includes a resistive switching device and anon-linear device serially coupled to the resistive switching device. Ina specific embodiment, the resistive switching device includes at leasta first electrode, a second electrode, and a resistive switchingmaterial. The resistive switching material includes a silicon materialin a specific embodiment. The first electrode includes at least a silvermaterial in a specific embodiment. The non-linear device is disposedbetween the second electrode and the resistive switching material in aspecific embodiment. In a specific embodiment, each of the memory cellshas a first current flowing in the respective resistive switchingdevice. The first current can be a dark current in each of the device ina specific embodiment. The method includes selecting a first memory celland applying a first voltage to the first memory cell. The first voltageis configured to cause the non-linear device, e.g., punch-through diode,to conduct current and to cause the resistive switching deviceassociated with the first memory cell to change from the first state toa second while the first current from other memory cells is blocked fromflowing in the first memory cell by a second voltage drop across therespective non-linear device in other memory cells.

According to one aspect of the invention, a non-volatile memory deviceis described. One device includes a resistive switching devicecomprising a first electrode, a second electrode, and a resistiveswitching element, wherein the resistive switching element comprises asilicon material disposed in an overlapping region between the firstelectrode and the second electrode, wherein the second electrodecomprises at least a metal material physically and electrically incontact with the resistive switching material, wherein the resistiveswitching element is characterized by a resistance depending on anelectric field in the resistive switching element. A device may includea non-linear device coupled between the first electrode and theresistive switching element, wherein the non-linear device is configuredto conduct electric current when a voltage greater than a first voltageis applied to the second electrode. In various embodiments, theresistive switching device is configured to change from a first state toa second state in response to the first voltage.

According to another aspect of the invention, a method of programming amemory cell in an array of non-volatile memory devices is described. Onetechnique includes providing a plurality of memory cells arranged in anarray, wherein each of the plurality of memory cells comprises aresistive switching device and a non-linear device serially coupled tothe resistive switching device, wherein each of the memory cells have afirst current flowing in respective resistive switching devices, whereinthe resistive switching device comprise at least a first electrode, asecond electrode, and a resistive switching material, wherein theresistive switching material comprises a silicon material, wherein thefirst electrode comprises at least a silver material, and wherein thenon-linear device is disposed in between the second electrode and theresistive switching material. A process may include selecting a firstmemory cell, and applying a first voltage to the first memory cell,wherein the first voltage is greater than a voltage to cause thenon-linear device to conduct a first current and to cause the resistiveswitching device associated with the first memory cell to change from afirst state to a second state, while a first current from other memorycells is blocked from flowing in the first memory cell by a secondvoltage drop across respective non-linear devices associated with othermemory cells.

Many benefits can be achieved by ways of present invention overconventional techniques. Embodiments according to the present inventionprovide a device structure and a programming method for a non-volatilememory device. The device structure includes a non-linear device tosuppress leakage current from interfering with write, erase as well asread operations in a specific embodiment. Depending on the embodiment,one or more of these benefits may be achieved. One skilled in the artwould recognize other variations, modifications, and alternatives.

SUMMARY OF THE DRAWINGS

In order to more fully understand the present invention, reference ismade to the accompanying drawings. Understanding that these drawings arenot to be considered limitations in the scope of the invention, thepresently described embodiments and the presently understood best modeof the invention are described with additional detail through use of theaccompanying drawings in which:

FIG. 1 is a simplified diagram illustrating a resistive switching deviceaccording to an embodiment of the present invention.

FIG. 2 is a simplified diagram illustrating a resistive switching devicearranged in a crossbar configuration according to an embodiment of thepresent invention.

FIGS. 3, 4, and 5 are simplified diagrams illustrating a resistiveswitching mechanism of the resistive switching device according to anembodiment of the present invention.

FIG. 6 is a simplified diagram illustrating a portion of a crossbararray and a leakage current path according to an embodiment of thepresent invention.

FIG. 7 is a simplified diagram illustrating a current-voltagecharacteristic of a conventional rectifying device.

FIG. 8 is a simplified diagram illustrating a non-linear deviceaccording to an embodiment of the present invention.

FIG. 9 is a simplified diagram illustrating a current-voltagecharacteristic of the non-linear device according to an embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

The present invention is directed to switching devices. Moreparticularly, embodiments of the present invention provide a method anddevice structure for a resistive switching device coupled to anon-linear device, e.g., diode, to prevent leakage current for properoperations of the resistive switching device. Embodiments of the presentinvention have been applied to a crossbar array of non-volatile memorydevice using a silicon material as resistive switching material. But itshould be recognized that embodiments of the present invention have abroader range of applicability.

High density and low cost storage devices are in ever increasing demanddue to the growth in consumer devices common in the market place.Current non-volatile memory devices including Flash are probablyapproaching an end to further scaling due to fundamental limitations inthe devices. It is predicted that current charge storage in a floatinggate or a dielectric material in Flash may not be possible in devicesize less that about 10 nm. A new category of devices using aninterconnected crossbar configuration that can be vertically integratedin a three dimensional manner provides a high device density notachievable in current memory devices.

However, leakage current from cells in an interconnected crossbar arraycan affect proper operations (read, write, or erase) of the device. Tosuppress the leakage current and to isolate a cell from the leakagecurrent, certain rectifiers can be used. A conventional rectifierusually limits current to flow in a single direction, and can only workfor a forward bias operation or a reverse bias operation and not forboth. Thus conventional rectifiers are of limited applicability. Certainswitching devices can have symmetrical current-voltage (IV) behavior,but such devices do not generally work well in a crossbar array. Otherrectifying devices may have a low on-state current but can have poordata retention characteristics. Embodiments of the present inventionprovide a device structure that includes at least a non-linear deviceand related methods for a resistive switching device that is rectifyingand yet allows current to flow in forward bias as well as in reversebias operations.

FIG. 1 is a simplified diagram illustrating a resistive switching device100 according to an embodiment of the present invention. The resistiveswitching device includes a first electrode 102, a second electrode 106,and a resistive switching material 104 sandwiched between the firstelectrode and the second electrode. As merely an example, the firstelectrode can be a first conductor material. The first electrode 102 caninclude a first conductive material such as a first metal material or adoped semiconductor material. In a specific embodiment, the first metalmaterial can be tungsten, aluminum, copper or other suitable metal thatis compatible with CMOS fabrication techniques. In a specificembodiment, the first electrode is elongated in shape and extends in afirst direction.

The resistive switching material 104 can include a suitable insulatormaterial having a resistance that can be altered upon application of anelectric field to the insulator material. In a specific embodiment, theresistive switching material can include a silicon material. Forexample, the silicon material can be an amorphous silicon material, amicrocrystalline silicon material, a macro crystalline silicon material,a silicon germanium material including any combination of thesematerials, or the like. In an embodiment, the silicon material includesan amorphous silicon material.

The second electrode 106 can comprise a second conductive material andcan have a portion that includes a second metal material. The secondmetal material can be aluminum, nickel, silver, gold, palladium,platinum, or another similar metal or combination of metals. The secondmetal material typically is characterized by a suitable diffusivity intothe resistive switching material in a specific embodiment. In a specificembodiment, the second electrode 106 is elongated in shape and extendsin a second direction that is orthogonal to the first direction, asillustrated in FIG. 2. In a specific embodiment, the second metalmaterial includes a silver material.

In certain embodiments, the resistive switching device further includesa contact material 108 disposed between the metal material of the firstelectrode 102 and the amorphous silicon material 104. The contactmaterial is believed to provide a suitable interfacial defectcharacteristic for desirable switching behavior for the resistiveswitching device. For amorphous silicon material as the resistiveswitching material, the contact material can be p+ polysilicon material,p+ silicon germanium material, or the like. In certain embodiments, thecontact material can be optional. The resistive switching device can bedisposed in an N by M crossbar array with pillars of resistive switchingmaterial 104 located at the crossings of the array, to form a highdensity interconnected array of non-volatile memory cells.

FIGS. 3-5 are simplified diagrams illustrating operations of a resistiveswitching device. As shown in FIG. 3, the second metal material forms ametal region 302 in a portion of the resistive switching material 104when a first positive voltage 304 greater than a threshold voltage isapplied to the second electrode 106. The threshold voltage is theforming voltage for the resistive switching device. In thisconfiguration, the resistive switching device is at a high resistancestate, otherwise known as an erase state, or an “OFF” state.

As shown in FIG. 4, the metal region may further form a filament region402. The filament region 402 may be characterized by a length, a firstdistance between metal particles, a second distance between the filamentand the first electrode 102, and the like. In FIG. 4, the filamentextends in a direction 404 towards the first electrode 102 when a secondpositive bias voltage 406 is applied to the second electrode 106. Inthis configuration the resistive switching device 104 is in a lowresistance state, otherwise known as a programmed or “ON” state,allowing current to flow through the resistive switching device 104.

As illustrated in FIG. 5, the filament structure 402 retracts in adirection 502 away from first electrode 102, when a negative biasvoltage 504 or an erase voltage is applied to the second electrode 106.In this configuration, the resistive switching device 104 is revertedback to the high resistance state illustrated in FIG. 3. Accordingly, asshown in FIGS. 3-5. the resistive switching device 100 is considered atwo-terminal or a bipolar device.

Due to the interconnectivity of a crossbar structure, when an operatingvoltage (e.g. e.g. the second positive bias voltage 406) is applied to aselected cell, leakage current from un-selected cells can form a leakagepath, that affects operations of the selected cell. Leakage current fromthe selected cell can also affect the states of unselected cells in theleakage path. As an example of this, in a situation where a selectedcell is at a high conductance state, leakage current from the highconductance cell can erase an unselected cell also in the highconductance state in the leakage path.

FIG. 6 is a simplified diagram illustrating a crossbar array of memorycells 600. Four cells 602, 604, 608, and 610 are illustrated. Cell 602includes a first bottom electrode 612, a first top electrode 614, and afirst resistive switching region 618. Cell 604 shares the same firstbottom electrode 612 as cell 602, and includes a second top electrode616 and a second resistive switching region 620. Cell 608 shares thesame first top electrode 614 as cell 602, and includes a third bottomelectrode 622 and a third resistive switching region 624. Cell 610shares the same first top electrode 616 as cell 602, and the same bottomelectrode 622 as cell 608 and a fourth resistive switching region 628.

An example of a programming operation of an embodiment will now bedescribed with respect to FIG. 6 using cell 602 as a target cell forprogramming. In the programming operation, a positive bias voltageapplied to first top electrode 614 causes cell 602 to be in a lowresistance state, such that an ‘ON’ state current flows in cell 602during a subsequent read operation. If cell 604 is in a low resistance(e.g. programmed state) , current leaking from cell 602 can cause cell604 to be unintentionally erased. Similarly, if cell 602 is in aprogrammed state and to be erased, a negative voltage applied to firsttop electrode 614 can cause cell 608 to be unintentionally erased whencell 608 is in a low resistance state.

In various embodiments, to prevent or reduce the incidence of theleakage current from affecting operations of the selected cell or tomaintain a state of an unselected cell, a rectifier or a diode may beincorporated into the design.

FIG. 7 illustrates a conventional diode 700 and an IV characteristic 702of the conventional diode. Because a conventional diode limits currentflow only in one direction, the conventional diode can only reducereverse current flow for either a program operation (e.g. positivevoltage) or an erase operation (e.g. negative voltage) , but typicallynot for both. In particular, if the conventional diode allows current toflow in a forward bias (for example, in a programming operation), theconventional diode may experience breakdown in reversed bias or duringan erase operation when a current starts to flow. Similarly, aconventional diode configured to operate for a negative bias erasefunction may experience breakdown during a positive bias programfunction. After breakdown, the conventional diode becomes defective andnon-functional.

Embodiments according to the present invention provide a device coupledto a resistive switching device, as described above, that addresses thisbreakdown issue. In various embodiments, the non-linear device is a twoterminal device configured to prevent leakage current from unselectedcells to interfere with proper operation of a selected cell underconditions of forward bias as well as reversed bias. The non-lineardevice also prevents leakage current from a selected cell during, forexample programming, from unintentionally erasing one or more unselectedcells or unintentionally programming one or more unselected cells. Invarious embodiments, the non-linear device is serially connected to theresistive switching device and can be disposed between the firstelectrode (FIG. 1, 106) and the resistive switching element (FIG. 1,104) in a specific embodiment. In other embodiments, the non-lineardevice can be disposed between the second electrode 106 and theresistive switching element (104, 108). In a specific embodiment, thenon-linear device is configured to conduct electric current when anoperating voltage is applied to, for example, the second electrode 106of the resistive switching device 100. The operating voltage includes aforward biased programming voltage and a reverse biased erase voltage ina specific embodiment.

Referring to FIG. 8, in a specific embodiment, the non-linear device 800includes a first impurity region 802, a second impurity region 804, anda third impurity region 806 sandwiched between the first impurity region802 and the second impurity region 806. In various embodiments, thefirst impurity region 802 and the second impurity region 804 have thesame charge polarity characteristic and have substantially the sameimpurity concentration. The third impurity region 806 has an oppositecharge polarity characteristic and a lower impurity concentration thanthe first impurity region 802 and the second impurity region 804. Forexample, as shown in FIG. 8, the non-linear device can have a pnpconfiguration or an npn configuration depending on the embodiment.

In operation, the non-linear device 800 is configured to conductelectric current when a voltage greater than a first voltage, or“punch-through” voltage, is applied. This type of diode may be referredto as a punch-through diode. The first voltage further causes theresistive switching device to change from a first state (e.g.non-conductive) to a second state (e.g. conductive). For example, thefirst state can be an off state or a high resistance state and thesecond state can be a programmed state or a low resistance state. Invarious embodiments, the first voltage can be a programming voltage or aread voltage depending on the embodiment. Embodiments according to thepresent invention can be applied to a one-time programmable memorydevice configured in an array, for example in a crossbar array.

Referring again to FIG. 8, in various embodiments, the non-linear device800 includes a first depletion region 808 formed from the first impurityregion 802 and the third impurity region 806, and a second depletionregion 810 formed from the second impurity region 804 and the thirdimpurity region 806. When a first voltage is applied to a selected cell,(for example, in a programming operation or an erase operation), thefirst depletion region 808 and the second depletion region 810 expand,as illustrated. At a high enough voltage (for example, the firstvoltage), the two depletion regions (808 and 810) merge, so that afurther increase in applied voltage would allow a current to flow andcause switching in the resistive switching device. In such a case, asvoltage drop across an unselected cell is low, depletion regions of anon-linear device of the unselected cell do not expand, and little ifany current flows through the unselected cell. An exemplifiedcurrent-voltage (IV) characteristic of the non-linear device isillustrated in FIG. 9.

Other embodiments of the present invention may include variations towhat is illustrated and described above. For example, the non-lineardevice can have an insulator material sandwiched between a first metaland a second metal or having a metal-insulator-metal (MIM)configuration. The non-linear device can also have a first insulatormaterial and a second insulator material sandwiched between the firstmetal and the second metal or a metal-insulator-insulator-metal(M-I-I-M) configuration depending on the application. Again, the diodehaving MIM or MIIM configuration can be disposed between the resistiveswitching element and the first electrode. And alternatively, thenon-linear device having MIM or MIIM configuration can be disposedbetween the resistive switching element and the second electrode,depending on the application.

The present invention has been exemplified using silver electrode andamorphous silicon material as resistive switching material. Thenon-linear device can be applied to any two terminal devices to preventleakage current from proper operation of the two terminal device.Therefore though the present invention has been described using variousexamples and embodiments, it is also understood that the examples andembodiments described herein are for illustrative purposes only and thatvarious modifications or alternatives in light thereof will be suggestedto persons skilled in the art and are to be included within the spiritand purview of this application and scope of the appended claims.

1-22. (canceled)
 23. A method for a memory device from an array ofmemory devices comprising a first bottom electrode and a second bottomelectrode, a first top electrode and a second top electrode, a firstmemory cell disposed between the first bottom electrode and the firsttop electrode, a second memory cell disposed between the first bottomelectrode and the second top electrode, a third memory cell disposedbetween the second bottom electrode and the first top electrode, and afourth memory cell disposed between the second bottom electrode and thesecond top electrode, wherein each memory device from the array ofmemory devices comprises a resistive switching material in series with anon-linear device, wherein the non-linear device includes asubstantially conductive and a substantially non-conductive state, themethod including: applying a read voltage between the first topelectrode and the first bottom electrode to cause a non-linear device ofthe first memory cell to be in the substantially conductive state,wherein a non-linear device of the second memory cell remains in thesubstantially non-conductive state, wherein a non-linear device of thethird memory cell remains in the substantially non-conductive state, andwherein a non-linear device of the second memory cell remains in thesubstantially non-conductive state; and determining a current flowbetween the first top electrode and the first bottom electrode inresponse to the read voltage.
 24. The method of claim 23 whereindetermining the current flow comprises: determining a current flowthrough the resistive switching material in response to the readvoltage.
 25. The method of claim 24 wherein the current flow through theresistive switching material is high when the resistive switchingmaterial is in a programmed state; and wherein the current flow throughthe resistive switching material is low when the resistive switchingmaterial is in an erase state.
 26. The method of claim 23 furthercomprising applying an erase voltage between the first top electrode andthe first bottom electrode to cause the non-linear device of the firstmemory cell to be in the substantially conductive state and to cause aresistive switching material in the first memory cell to enter ormaintain an erase state in response to the erase voltage, wherein thenon-linear device of the second memory cell remains in the substantiallynon-conductive state, wherein the non-linear device of the third memorycell remains in the substantially non-conductive state, and wherein thenon-linear device of the fourth memory cell remains in the substantiallynon-conductive state.
 27. The method of claim 23 further comprisingapplying a programming voltage between the first top electrode and thefirst bottom electrode to cause the non-linear device of the firstmemory cell to be in the substantially conductive state and to cause aresistive switching material in the first memory cell to enter ormaintain a programmed state in response to the programming voltage,wherein the non-linear device of the second memory cell remains in thesubstantially non-conductive state, wherein the non-linear device of thethird memory cell remains in the substantially non-conductive state, andwherein the non-linear device of the fourth memory cell remains in thesubstantially non-conductive state.
 28. The method of claim 23 whereinthe resistive switching material is selected from a group consisting of:an amorphous silicon material, a microcrystalline silicon material, amacro crystalline silicon material, a silicon germanium material. 29.The method of claim 23 wherein the first top electrode is selected froma group consisting of: aluminum, nickel, silver, gold, palladium, andplatinum.
 30. The method of claim 23 further comprising applying theread voltage between the second top electrode and the first bottomelectrode to cause the non-linear device of the second memory cell to bein the substantially conductive state, wherein the non-linear device ofthe first memory cell remains in the substantially non-conductive state,wherein the non-linear device of the third memory cell remains in thesubstantially non-conductive state, and wherein the non-linear device ofthe second memory cell remains in the substantially non-conductivestate; and determining a current flow between the second top electrodeand the first bottom electrode in response to the read voltage.
 31. Themethod of claim 23 further comprising applying the erase voltage betweenthe first top electrode and the second bottom electrode to cause thenon-linear device of the third memory cell to be in the substantiallyconductive state and to cause the resistive switching material in thethird memory cell to enter or maintain an erase state in response to theerase voltage, wherein the non-linear device of the second memory cellremains in the substantially non-conductive state, wherein thenon-linear device of the first memory cell remains in the substantiallynon-conductive state, and wherein the non-linear device of the fourthmemory cell remains in the substantially non-conductive state.
 32. Themethod of claim 23 further comprising applying the programming voltagebetween the second top electrode and the second bottom electrode tocause a non-linear device of the fourth memory cell to be in thesubstantially conductive state and to cause a resistive switchingmaterial in the fourth memory cell to enter or maintain a programmedstate in response to the programming voltage, wherein the non-lineardevice of the second memory cell remains in the substantiallynon-conductive state, wherein the non-linear device of the third memorycell remains in the substantially non-conductive state, and wherein thenon-linear device of the first memory cell remains in the substantiallynon-conductive state.
 33. A device including an array of memory devicescomprising a plurality of bottom electrodes including a first bottomelectrode and a second bottom electrode; a plurality of top electrodescomprising a metal material including a first top electrode comprisingand a second top electrode; a plurality of memory cells disposed betweenthe plurality of bottom electrodes and the plurality of top electrodes,wherein the plurality of memory cells includes a first memory cell, asecond memory cell, a third memory cell and a fourth memory cell,wherein each memory cell from the plurality of memory cells comprises aresistive switching material layer coupled in series with a non-lineardevice, wherein the resistive switching material layer is electricallyconnected to the metal material of one of the plurality of topelectrodes, wherein the resistive switching material is associated witha variable resistance, wherein the non-linear device is associated witha substantially conductive or a substantially non-conductive state,wherein the first memory cell is disposed between the first bottomelectrode and the first top electrode, wherein the second memory cell isdisposed between the first bottom electrode and the second topelectrode, wherein the third memory cell is disposed between the secondbottom electrode and the first top electrode, and wherein the fourthmemory cell is disposed between the second bottom electrode and thesecond top electrode; wherein when a read voltage is applied between thefirst top electrode and the first bottom electrode, a non-linear deviceof the first memory cell is in the substantially conductive state, anon-linear device of the second memory cell is in the substantiallynon-conductive state, a non-linear device of the third memory cell is inthe substantially non-conductive state, a non-linear device of thefourth memory cell is in the substantially non-conductive state, and acurrent flows between the first top electrode and the first bottomelectrode in response to a resistance of a resistive switching materiallayer of the first memory cell.
 34. The device of claim 33 wherein thecurrent flow between the first top electrode and the first bottomelectrode is higher when the resistive switching material layer of thefirst memory cell is in a programmed state than when the resistiveswitching material layer of the first memory cell is in an erase state.35. The device of claim 33 wherein when a program voltage is appliedbetween to the first top electrode and the first bottom electrode, thenon-linear device of the first memory cell is in the substantiallyconductive state, the non-linear device of the second memory cell is inthe substantially non-conductive state, the non-linear device of thethird memory cell is in the substantially non-conductive state, thenon-linear device of the fourth memory cell is in the substantiallynon-conductive state, and the resistive switching material layer of thefirst memory cell enters or maintains the programmed state.
 36. Thedevice of claim 35 wherein when an erase voltage is applied between tothe first top electrode and the first bottom electrode, the non-lineardevice of the first memory cell is in the substantially conductivestate, the non-linear device of the second memory cell is in thesubstantially non-conductive state, the non-linear device of the thirdmemory cell is in the substantially non-conductive state, the non-lineardevice of the fourth memory cell is in the substantially non-conductivestate, and the resistive switching material layer of the first memorycell enters or maintains the erase state.
 37. The device of claim 36wherein the programmed state of the resistive switching material layerof the first memory cell is associated with a lower resistance than theerase state of the resistive switching material layer of the firstmemory cell.
 38. The device of claim 33 wherein the resistive switchingmaterial layer comprises a material selected from a group consisting of:an amorphous silicon material, a microcrystalline silicon material, amacro crystalline silicon material, a silicon germanium material. 39.The device of claim 33 wherein the metal material of the plurality oftop electrodes are selected from a group consisting of: aluminum,nickel, silver, gold, palladium, and platinum.
 40. The device of claim33 wherein the non-linear device comprises a metal-insulator-metalconfiguration.
 41. The device of claim 40 wherein the non-line device ofthe first memory cell is disposed between the resistive switchingmaterial layer of the first memory cell and the first bottom electrode.42. The device of claim 33 wherein the non-linear device comprises ametal-insulator-insulator-metal configuration.
 43. A method for a memorydevice from an array of memory cells comprising a plurality of bottomelectrodes including bottom electrode and a second bottom electrode, aplurality of top electrodes including a first top electrode and a secondtop electrode, wherein memory cells from the array of memory cells eachcomprise a resistive switching material in series with a non-lineardevice, wherein each memory device from the array of memory devicescomprises a resistive switching material in series with a non-lineardevice, wherein the array of memory cells includes a first memory celldisposed between the first bottom electrode and the first top electrode,a second memory cell disposed between the first bottom electrode and thesecond top electrode, a third memory cell disposed between the secondbottom electrode and the first top electrode, and a fourth memory celldisposed between the second bottom electrode and the second topelectrode, wherein the non-linear device is characterized by asubstantially conductive or a substantially non-conductive state, themethod including: applying a programming voltage between the first topelectrode and the first bottom electrode to cause a non-linear device ofthe first memory cell to be in the substantially conductive state and tocause the resistive switching material in the first memory cell to enteror maintain a programmed state in response to the programming voltage,wherein a non-linear device of the second memory cell remains in thesubstantially non-conductive state, wherein a non-linear device of thethird memory cell remains in the substantially non-conductive state, andwherein a non-linear device of the fourth memory cell remains in thesubstantially non-conductive state.
 44. The method of claim 43 furthercomprising: applying an erase voltage between the first top electrodeand the first bottom electrode to cause a non-linear device of the firstmemory cell to be in the substantially conductive state and to cause theresistive switching material in the first memory cell to enter ormaintain an erase state in response to the erase voltage, wherein thenon-linear device of the second memory cell remains in the substantiallynon-conductive state, wherein the non-linear device of the third memorycell remains in the substantially non-conductive state, and wherein thenon-linear device of the fourth memory cell remains in the substantiallynon-conductive state.